The present invention relates to a PLL (Phase-Locked Loop) circuit, and in particular, to a PLL circuit that can reduce the number of false locks than a conventional PLL circuit for a signal that is read from a storage medium such as an MO disk (Magneto-Optical disk), a CD (Compact Disk), an MD (Mini Disk), and HD (Hard Disk), and further can perform locking (synchronizing) operation faster than before.
A decoding apparatus configured by including a conventional PLL circuit will be described with reference to FIG. 10.
This decoding apparatus comprises a gain controller 10 receiving a read signal from an MO, a CD, an MD, an HD, or the like as an input signal and performing desired amplifying operation for this input signal, an equalizing filter 20 filtering an output of this gain controller 10,. a PLL circuit 100, and a Viterbi decoding circuit 80 outputting a Viterbi decoding result.
The PLL circuit 100, as shown in FIG. 10, comprises an A/D converter 30 performing the A/D conversion of an output of the equalizing filter 20, a phase difference calculating unit 40 obtaining phase difference on the basis of an output from this A/D converter 30, a D/A converter 50 for performing the D/A conversion of this phase difference and outputting it, a loop filter 60 for integrating an output of the D/A converter 50, and a VCO (Voltage Controlled Oscillator) 70 for generating a sampling clock according to an integrated signal.
Each component of this PLL circuit 100 configures a PLL loop as a whole, and by this PLL loop, phase pulling-in operation is performed so that phase difference obtained in the phase difference calculating unit 40 becomes xe2x80x9czeroxe2x80x9d. In addition, the sampling operation of the A/D converter 30 is performed with synchronizing with the sampling clock from the VCO 70.
Next, the operation of the PLL circuit 100 having such configuration will be described with reference to drawings.
When an analog signal shown in FIG. 11(a) is given, the A/D converter 30 generates sampled values by sampling the analog signal as well as synchronizing with the rise of the sampling clock from VCO 70 that is shown in FIG. 11(b), and outputs this sampled values. A round mark in FIG. 11(a) shows a sampling point, and its numeric value shows a concrete sampled value. The phase difference calculating unit 40 obtains phase difference between the above-described input analog signal and sampling clock from the next formula (1) on the basis of four sampled values obtained as described above.
Phase difference={Smpl+(xe2x88x92+)xe2x88x92Smpl+(+xe2x88x92)}+{Smplxe2x88x92(xe2x88x92+)xe2x88x92Smplxe2x88x92(+xe2x88x92)}xe2x80x83xe2x80x83formula (1)
Here, in formula (1), Smpl+(xe2x88x92+) is a positive sampled value when digital sampling values change from a negative (xe2x88x92) to a positive (+), Smpl+(+xe2x88x92) is a positive sampled value when sampled values change from a positive to a negative, Smplxe2x88x92(xe2x88x92+) is a negative sampled value when sampled values change from a negative to a positive, and Smplxe2x88x92(+xe2x88x92) is a negative sampled value when sampled values change from a positive to a negative.
The phase difference calculating unit 40 obtains phase difference by formula (1) by using this new value whenever newly taking two sampled values in, and updates a value of the phase difference in turn. This phase difference obtained is digital-analog converted by the D/A converter 50, and is integrated by the loop filter 60, this integrated signal becomes a control signal for the VCO 70, and by this control signal, an oscillation frequency of the VCO 70 is controlled at any time.
At this time, if the relation between the input analog signal in A/D converter 30 and the sampling clock from the VCO 70 is as shown in FIG. 11, phase difference by formula (1) becomes xe2x80x9czeroxe2x80x9d, and hence sampling operation with the sampling clock is performed accurately.
On the other hand, if the relation between the input analog signal and sampling clock is as shown in FIG. 12, with obtaining phase difference by formula (1) by using sampled values in the drawing, the phase difference becomes a positive value as phase difference=(7xe2x88x923)+(xe2x88x923xe2x88x92(xe2x88x927))=8, and hence the sample timing of the input analog signal is in a late condition. Thus, feedback operation that advances a phase of the sampling clock is performed.
In addition, if the relation between the input analog signal and sampling clock is as shown in FIG. 13, with obtaining phase difference by formula (1) by using sampled values in the drawing, the phase difference becomes a negative value as phase difference=(3xe2x88x927)+(xe2x88x927xe2x88x92(xe2x88x923))=xe2x88x928, and hence the sample timing of the input analog signal is in an advanced condition. Thus, feedback operation that delays a phase of the sampling clock is performed. If such a feedback control is performed, feedback is performed so that a value of phase difference in formula (1) finally becomes zero, thereby completing pulling-in operation, and performing locking operation.
By the way, as a conventional synchronization method that is different from the above-described one, for example, a method is proposed, the method generating a sampling clock so that edges of the sampling clock correspond to zero-cross points (points where a signal becomes zero) of the input analog signal shown in FIG. 11(a). Nevertheless, in this synchronization method, it becomes necessary to adopt an edge-pulling-in type PLL circuit instead of the PLL loop shown in FIG. 10, and to further use other circuit elements such as a delay element. This type of PLL circuit is called an analog type PLL, which cannot perform precise pulling-in operation if the phase pulling-in operation is necessary for data after digital conversion of a signal like a PRML (Partial Response Maximum Likelihood) method.
Furthermore, there is a method of providing two groups of PLL loops each including the A/D converter 50, loop filter 60 and VCO 70, which are shown in FIG. 10, for accelerating phase (including a frequency) pulling-in speed, one PLL loop of which has a gain that is as high as possible at the time of pulling-in, and another PLL loop of which has a gain that is set low for stabilizing the loop as much as possible after pulling-in.
However, in the conventional PLL circuits, false lock 10 explained below occurs, and hence the performance of the PLL circuits deteriorates remarkably.
What is shown in FIG. 14 is a case that a frequency of the input signal is a desired value but sampling points are not at desired positions and Smplxe2x88x92(+xe2x88x92) and Smplxe2x88x92(xe2x88x92+) correspond to the same sampling point, and hence the operation result of formula (1) becomes xe2x80x9czeroxe2x80x9d, and the phase difference becomes xe2x80x9czeroxe2x80x9d. In this case, a state of feedback control by a PLL loop unintentionally becomes stable at a state that the feedback control should not be essentially stable, and hence the false lock (the first false lock) occurs.
A situation which is the same as this will be explained more concretely with reference to FIG. 15. If sampling points of the input signal become as shown in FIG. 15, it is only judged in the conventional technology that sampling points are before or after zero cross, and sampled values are assigned to respective term of formula (1). Owing to this, the phase difference obtained by formula (1) from concrete numeric values shown in FIG. 15 (sampled values) is Phase difference=(Cxe2x88x92A)+(Bxe2x88x92B)=(2xe2x88x922)+(xe2x88x926xe2x88x92(xe2x88x926))=0. In this manner, if the phase difference becomes xe2x80x9czeroxe2x80x9d, feedback control by the PLL loop becomes not effective, and hence there is a possibility that the feedback control becomes stable in a wrong phase.
In addition, what is shown in FIG. 16 is false lock occurring when frequencies of the sampling clock from the VCO 70 are slower than a frequency of the input signal. FIG. 15(a) shows a case that an oscillation frequency (fvco) of the VCO 70 synchronizes with the input signal and hence accurate sampling is performed. FIGS. 16(b) and 16(c) show cases that frequencies of sampling clocks from the VCO 70 are slower than the frequency of the input signal (two times slower than the usual in FIG. 16(b), and six times slower than the usual in FIG. 16(c).
In this case, for example, as shown in FIG. 16 (b), if digital sampling is performed at positive and negative peak positions of the input signal, Smplxe2x88x92(+xe2x88x92) and Smplxe2x88x92(xe2x88x92+) correspond to the same sampling point, the operation result of formula (1) becomes xe2x80x9c0xe2x80x9d, and hence the phase difference becomes xe2x80x9czeroxe2x80x9d. Therefore, also owing to this, the false lock (the second false lock) occurs.
By the way, there is also a case that an input signal to the A/D converter 30 has an offset, and in such a case, sampling points are shifted, there is a possibility of false lock occurring, and hence it is desirable to reduce the offset of the input signal as much as possible.
As described above, in order to prevent the occurrence of the false lock, it is necessary to provide a circuit to perform pulling-in operation by bringing an oscillation frequency of the VCO close to an expected frequency of the input signal till the pulling-in operation by the PLL loop is started, and a circuit to reduce the offset. Nevertheless, evils are conceivable, the evils which cause cost increase due to complexity of circuitry and deteriorate the capability of the entire system.
The present invention has been achieved in order to solve such conventional problems, and its first object is to provide a PLL circuit which can prevent the above-described false lock with simple configuration.
In addition, a second object of the present invention is to provide a PLL circuit that can not only prevent the above-described false lockwith simple configuration, but also reduce an offset of an input signal.
The present invention provides a PLL circuit including: an A/D converter for obtaining sampled values in turn by sampling an analog signal as well as synchronizing with a sampling clock; a phase difference detecting circuit for obtaining phase difference between the above-described analog signal and the above-described sampling clock on the basis of the above-described sampled values; a loop filter for integrating the above-described phase difference; and an voltage controlled oscillator for controlling the timing of the above-described sampling clock according to the above-described phase difference integrated, characterized in that the above-described phase difference detection circuit obtains the above-described phase difference according to a predetermined operational expression by using a predetermined number of sampled values, obtains a sign pattern of the above-described predetermined number of sampled values, and determines input values to the above-described operational equation according to this obtained sign pattern.
As an embodiment of a PLL circuit of the present invention, a PLL circuit can be cited, the PLL circuit characterized in that the above-described phase difference detecting circuit has a table that describes the relation between the above-described sign patterns and input values to the above-described operational equation, and determining input values to the above-described operational equation by referring to the above-described sign patterns and the above-described table.
As another embodiment of a PLL circuit of the present invention, a PLL circuit is cited, the PLL circuit being characterized in that the above-described phase difference detecting circuit comprises: a register for storing sampled values from the above-described A/D converter in turn; a code judging section that obtains a sign pattern of the predetermined number of sampled values stored in this register, and determines according to this sign pattern, which is obtained, whether processing contents are updated to redetermined sampled values as input values to the above-described operational equation or not updated; and a calculating section for obtaining the above-described phase difference according to the above-described operational equation on the basis of the determination of this code judging section.
As an embodiment of a PLL circuit of the present invention, a PLL circuit is cited, the PLL circuit being characterized in that the above-described predetermined number of sampled values is a predetermined number of newest sampled values and sampled values before that.
As an embodiment of a PLL circuit of the present invention, a PLL circuit is cited, the PLL circuit being characterized in that the above-described predetermined number of sampled values are four including a newest value, and a number of the above-described past sampled values is two lasting to the newest four.
As an embodiment of a PLL circuit of the present invention, a PLL circuit is cited, the PLL circuit being characterized in that the above-described phase difference detecting circuit comprises: a first register for storing sampled values from the above-described A/D converter in turn; a second register for storing a state corresponding to a sign pattern of sampled values stored in this first register; a code judging section for determining whether processing contents are to be updated in predetermined sampled values, stored in the above-described first register, as input values to the above-described operational equation according to a sign pattern of a predetermined number of newest sampled values stored in the above-described first register and the state stored in the above-described second register, or are not to be updated; and a calculating section for obtaining the above-described phase difference according to the above-described operational equation on the basis of the determination of this code judging section.
As an embodiment of a PLL circuit of the present invention, a PLL circuit is cited, the PLL circuit being characterized in that the state that is stored in the above-described second register is any one of a state that a sign pattern is normal, a state that the sign pattern is abnormal, and a state that the sign pattern is not fixed to any one of the above-described states.
As an embodiment of a PLL circuit of the present invention, a PLL circuit is cited, the PLL circuit being characterized in that the above-described analog signal has a 2T pattern, and an operational equation for obtaining the above-described phase difference is Phase difference={Smpl+(xe2x88x92+)xe2x88x92Smpl+(+xe2x88x92)}+{Smplxe2x88x92(xe2x88x92+)xe2x88x92Smplxe2x88x92(+xe2x88x92)} (where, Smpl+(xe2x88x92+) denotes a positive sampled value when a sign of a digital signal sampled changes from a negative sign to a positive sign, Smpl+(+xe2x88x92) denotes a positive sampled value when a sign of the digital signal sampled changes from a positive sign to a negative sign, Smplxe2x88x92(xe2x88x92+) denotes a negative sampled value when a sign of the digital signal sampled changes from a negative sign to a positive sign, and Smplxe2x88x92(+xe2x88x92) denotes a negative sampled value hen a sign of the digital signal sampled changes from a positive sign to a negative sign).
As an embodiment of a PLL circuit of the present invention, a PLL circuit is cited, the PLL circuit being characterized in that, if the above-described sign pattern is xe2x80x9c+xe2x88x92+xe2x88x92xe2x80x9d or xe2x80x9cxe2x88x92+xe2x88x92+,xe2x80x9d the above-described code judging section does not perform the update processing of phase difference even if there is a change of signs of sampled values.
As an embodiment of a PLL circuit of the present invention, a PLL circuit is cited, the PLL circuit being characterized in that the above-described code judging section updates input values to the above-described operational equation to predetermined sampled values only when the above-described sign pattern is predetermined.
As an embodiment of a PLL circuit of the present invention, a PLL circuit is cited, the PLL circuit being characterized in that, if the above-described sign pattern is xe2x80x9c++xe2x88x92xe2x88x92xe2x80x9d or xe2x80x9cxe2x88x92xe2x88x92++,xe2x80x9d furthermore xe2x80x9c+xe2x88x92++xe2x80x9d or xe2x80x9cxe2x88x92+xe2x88x92xe2x88x92,xe2x80x9d that is regarded as a pattern similar to the concerned pattern, or moreover a pattern whose phase is shifted from this similar pattern, input values to the above-described operational equation are updated to predetermined sampled values even if there is not a sign change between two sampled values that are the newest.
In addition, the present invention provides a PLL circuit being characterized in that the PLL circuit comprises: any one of the above-described PLL circuits; offset detecting means for detecting an offset of the above-described analog signal by performing predetermined calculation for a plurality of sampled values outputted in turn from the above-described A/D converter; and offset canceling means for generating a signal canceling an offset detected by this offset detecting means and supplying this signal to an input side of the above-described A/D converter.